Planar process · TechGene

Definition

A semiconductor fabrication process that retains a protective silicon dioxide layer on the silicon surface and uses masks to form devices and interconnections.

What it is

The planar process forms and retains a silicon dioxide layer on the surface of a silicon wafer, opens windows through photolithography, and then carries out diffusion, oxidation, and metal deposition. Device junctions are protected beneath the planar structure, while metal lines above the insulating layer can connect different devices.

Why it emerged and what problems it solved

The junctions in early mesa structures were exposed at the surface and vulnerable to contamination and damage. Hoerni's planar method made the oxide a protective layer while retaining its roles as a mask and insulator, improving reliability and enabling wafer-level fabrication.

Why it matters and what it enabled

The planar process and Noyce's concept of metal interconnections together formed the fabrication foundation of modern monolithic integrated circuits. It transformed the goal of a better transistor into an industrial approach for manufacturing and connecting many transistors on the same wafer.

Principles and impact

Problems solved

Protects exposed p–n junctions, reducing failures caused by surface contamination and leakage.
Allows multiple devices to be fabricated and interconnected on the same wafer surface.

Principles

The oxide acts as a protective film and mask, with windows opened only where needed.
Diffusion, photolithography, and metal deposition are carried out layer by layer from the same side of the wafer.

Improvements

Improves transistor reliability, leakage characteristics, and consistency in batch production.
Combines device fabrication and metal interconnection in a monolithic process.

Significance

Connected silicon transistors with manufacturable monolithic integrated circuits.
Became the foundation for later MOS, large-scale integration, and microprocessor fabrication.

History and applications

People

Jean Hoerni、Robert Noyce、Jay Last

Organizations

Fairchild Semiconductor

Events

Hoerni proposed the planar fabrication process in 1959、Fairchild produced planar integrated circuits in 1960

Applications

Planar silicon transistors、Monolithic logic integrated circuits、MOS and CMOS chips

Limitations

Requires strict control of oxide layers, doping, defects, and alignment across layers.
As process complexity increases, yield and equipment costs become major constraints.

Upstream and downstream relations

Upstream

←Semiconductor photolithographyenabled byPhotolithography and masks transfer patterns for surface openings onto wafers, enabling the planar process to repeatedly form protected device regions.

Sources: 1959: Invention of the Planar Manufacturing Process

←Silicon transistorevolved fromThe planar process retains a protective silicon dioxide layer, improving manufacturing methods to address reliability problems at the surface junctions of silicon transistors.

Sources: 1959: Invention of the Planar Manufacturing Process

Downstream

→Integrated circuitsrequired byEarly manufacturable approaches to modern monolithic integrated circuits relied on the planar process for device isolation and surface interconnections.

Sources: Fairchild's Approach: The Planar Process

→MOS integrated circuitevolved intoMOS integrated circuits adopt the planar process's approaches to surface oxidation, masking, and interconnection, while further increasing device density.

Sources: 1964: First Commercial MOS IC Introduced 1959: Invention of the Planar Manufacturing Process

→Integrated circuitsapplied inThe planar process allows multiple devices to be formed on the surface of the same wafer and provides a flat, protected surface for subsequent metal interconnects.

Sources: Fairchild's Approach: The Planar Process Invention of the Planar Integrated Circuit & Other Stories from the Fairchild Notebooks